View CY7C1307V25_6420118.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary 18 mb burst of 4 pipelined sram with qdr architectu re cy7c1305v2 5 cy7c1307v2 5 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05099 rev. *a revised december 11, 2002 1305v25 features ? separate independent read and write data ports ? supports concurrent transactions 167 mhz clock for high bandwidth ? 2.5 ns clock-to-valid access time 4-word burst for reducing the address bus frequency double data rate (ddr) interfaces on both read & write ports (data transferred at 333 mhz) @167 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two output clocks (c and c ) accounts for clock skew and flight time mis-matches single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes 2.5v core power supply with hstl inputs and outputs 13x15 mm 1.0 mm pitch fbga package, 165 ball (11x15 matrix) variable drive hstl output buffers expanded hstl output voltage (1.4v?1.9v) jtag interface configurations cy7c1305v25 ? 1 mb x 18 CY7C1307V25 ? 512k x 36 functional description the cy7c1305v25/CY7C1307V25 are 2.5v synchronous pipelined srams equipped with qdr architecture. qdr ar- chitecture consists of two separate ports to access the mem- ory array. the read port has dedicated data outputs to sup- port read operations and the write port has dedicated data inputs to support write operations. qdr architecture has sep- arate data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus required with common i/o devices. access to each port is accomplished through a com- mon address bus. addresses for read and write addresses are latched on alternate rising edges of the input (k) clock. accesses to the device?s read and write ports are completely independent of one another. in order to maximize data throughput, both read and write ports are equipped with dou- ble data rate (ddr) interfaces. each address location is as- sociated with four 18-bit words (cy7c1305v25) and four 36-bit words (CY7C1307V25) that burst sequentially into or out of the device. since data can be transferred into and out of the device on every rising edge of both input clocks (k/k and c/c ) memory bandwidth is maximized while simplifying sys- tem design by eliminating bus ?turn-arounds.? depth expansion is accomplished with port selects for each port. port selects allow each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c input clocks. writes are con- ducted with on-chip synchronous self-timed write circuitry. logic block diagram (cy7c1305v25) 256kx18 array clk a (17:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 36 18 18 72 18 bws [0:1] vref write add. decode write reg 36 a (17:0) 18 c c 256kx18 array 256kx18 array 256kx18 array write reg write reg write reg 18
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 2 of 28 selection guide [1] 7c1305v25-200 7c1307v25-200 7c1305v25-167 7c1307v25-167 7c1305v25-133 7c1307v25-133 7c1305v25-100 7c1307v25-100 maximum operating frequency (mhz) 200 167 133 100 maximum operating current (ma) 500 450 350 230 note: 1. shaded areas contain advance information. logic block diagram (CY7C1307V25) 128k x 36 array clk a (16:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps q [35:0] control logic address register reg. reg. reg. 72 17 36 144 36 bws [0:3] vref write add. decode write reg 72 a (16:0) 17 c c 128k x 36 array 128k x 36 array 128k x 36 array write reg write reg write reg 36
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 3 of 28 pin configuration - cy7c1305v25 (top view) 1234567891011 a nc gnd/ 144m nc/ 36m wps bws 1 k nc rps a gnd/ 72m nc b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 vss a nc a vss nc q7 d8 d nc d11 q10 vss vss vss vss vss nc nc d7 e nc nc q11 vddq vss vss vss vddq nc d6 q6 f nc q12 d12 vddq vdd vss vdd vddq nc nc q5 g nc d13 q13 vddq vdd vss vdd vddq nc nc d5 h nc vref vddq vddq vdd vss vdd vddq vddq vref zq j nc nc d14 vddq vdd vss vdd vddq nc q4 d4 k nc nc q14 vddq vdd vss vdd vddq nc d3 q3 l nc q15 d15 vddq vss vss vss vddq nc nc q2 m nc nc d16 vss vss vss vss vss nc q1 d2 n nc d17 q16 vss a a a vss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdotckaaac aaatmstdi
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 4 of 28 pin configuration - CY7C1307V25 (top view) 1234567891011 a nc gnd/ 288m nc/ 72m wps bws 2 k bws 1 rps nc/36 m gnd/ 144m nc b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 vss a nc a vss d16 q7 d8 d d28 d20 q19 vss vss vss vss vss q16 d15 d7 e q29 d29 q20 vddq vss vss vss vddq q15 d6 q6 f q30 q21 d21 vddq vdd vss vdd vddq d14 q14 q5 g d30 d22 q22 vddq vdd vss vdd vddq q13 d13 d5 h nc vref vddq vddq vdd vss vdd vddq vddq vref zq j d31 q31 d23 vddq vdd vss vdd vddq d12 q4 d4 k q32 d32 q23 vddq vdd vss vdd vddq q12 d3 q3 l q33 q24 d24 vddq vss vss vss vddq d11 q11 q2 m d33 q34 d25 vss vss vss vss vss d10 q1 d2 n d34 d26 q25 vss a a a vss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdotckaaac aaatmstdi
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 5 of 28 pin definitions name i/o description d [x:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations. cy7c1305v25 ? d [17:0] CY7C1307V25 ? d [35:0]] wps input- synchronous write port select, active low. sampled on the rising edge of the k clock. when as- serted active, a write operation is initiated. deasserting will deselect the write port. deselecting the write port will cause d [x:0] to be ignored. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 - active low. sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1305v25 - bws 0 controls d [8:0] and bws 1 controls d [17:9]. CY7C1307V25 - bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] all the byte writes are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs. sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 1 mb x 18 (4 arrays each of 256k x 18) for cy7c1305v25 and 256k x 36 (4 arrays each of 128k x 36) for CY7C1307V25. there- fore, only 18 address inputs for cy7c1305v25 and 17 address inputs for CY7C1307V25.these inputs are ignored when the appropriate port is deselected. q [x:0] outputs- synchronous data output signals. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k . when in single clock mode. when the read port is deselected, q [x:0] are automatically three-stated. cy7c1305v25 - q [17:0] CY7C1307V25 - q [35:0] rps input- synchronous read port select, active low. sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will cause the read port to be deselected. when deselected, the pending access is allowed to complete and the out- put drivers are automatically three-stated following the next rising edge of the k clock. each read access consists of a burst of four sequential 18-bit or 36-bit transfers. c input-clock positive output clock, input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input-clock negative output clock, input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board cack to the controller. see application example for further details. k input-clock positive input clock, input. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input-clock negative input clock input. k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. zq input output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be con- nected directly to gnd or left unconnected.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 6 of 28 introduction functional overview the cy7c1305v25/CY7C1307V25 are synchronous pipe- lined burst srams equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs in order to minimize the number of address pins required. by having sep- arate read and write ports, the device completely eliminates the need to ?turn-around? the data bus and avoids any possible data contention, thereby simplifying system design. each ac- cess consists of four 18/36-bit data transfers in two clock cy- cles. accesses for both ports are initiated on the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the output clocks (c and c, or k and k when in single clock mode). all synchronous data inputs (d [x:0] ) inputs pass through input registers controlled by the input clocks (k and k ). all synchro- nous data outputs (q [x:0] ) outputs pass through output regis- ters controlled by the rising edge of the output clocks (c and c or k and k when in single clock mode). all synchronous control (rps , wps , bws [0:x] ) inputs pass through input registers. rps and wps are controlled by the rising edge of the input clock (k). bws [0:x] are controlled by the rising edges of input clocks (k and k ). the following descriptions take cy7c1305v25 as an exam- ple. however, the same is true for the other qdr sram, CY7C1307V25. read operations the cy7c1305v25 is organized internally as a 256kx72 sram. accesses are completed in a burst of four sequential 18-bit data words. read operations are initiated by asserting rps active at the rising edge of the positive input clock (k). the address presented to address inputs are stored in the read address register. following the next k clock rise the cor- responding lowest order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subse- quent rising edge of c the next 18-bit data word is driven onto the q [17:0] . this process continues until all four 18-bit data words have been driven out onto q [17:0] . the requested data will be valid 2.5ns from the rising edge of the output clock (c or c , 167 mhz device). in order to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and takes 2 clock cycles to complete. therefore, read accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device will ignore the second read request. read accesses can be initiated on every other k clock rise. doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (c and c, or k and k when in single clock mode). when the read port is deselected, the cy7c1305v25 will first complete the pending read transactions. synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the negative output clock (c). this will allow for a seamless transition between devices without the inser- tion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register provided bws [1:0] are both asserted active. this process continues for one more cy- cle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the mem- tdo output tdo for jtag. tck input tck pin for jtag. tdi input tdi pin for jtag. tms input tms pin for jtag. nc/36m input address expansion for 36m. this is not connected to the die. can be connected to any voltage level on cy7c1305v25/CY7C1307V25. gnd/72m input address expansion for 72m. this should be tied low on the cy7c1305v25 nc/72m input address expansion for 72m. this can be connected to any voltage level on CY7C1307V25 gnd/144m input address expansion for 144m. this should be tied low on cy7c1305v25/CY7C1307V25. gnd/288m input address expansion for 144m. this should be tied low on CY7C1307V25. v ref input- reference reference voltage input. static input used to set the reference level for hstl inputs and outputs as well as a/c measurement points. v dd power supply power supply inputs to the core of the device. should be connected to 2.5v power supply. v ss ground ground for the device. should be connected to ground of the system. v ddq power supply power supply inputs for the outputs of the device. should be connected to 1.5v power supply. nc nc no connect pin definitions
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 7 of 28 ory array at the specified location. therefore, write accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device will ignore the second write request. write accesses can be initiated on every other rising edge of the positive clock (k). doing so will pipeline the data flow such that 18-bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when deselected, the write port will ignore all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1305v25. a write operation is initiated as described in the write operation section above. the bytes that are written are determined by bws 0 and bws 1 which are sampled with each set of 18-bit data word. asserting the appropriate byte write select input during the data portion of a write will allow the data being pre- sented to be latched and written into the device. de-asserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modi- fy/write operations to a byte write operation. single clock mode the cy7c1305v25 can be used with a single clock that con- trols both the input and output registers. in this mode the de- vice will recognize only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew be- tween the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power-on. this function is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1305v25 operate com- pletely independently of one another. since each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. if the ports access the same location at the same time, the sram will deliver the most recent information asso- ciated with the specified address location. this includes for- warding data from a write cycle that was initiated on the pre- vious k clock rise. read accesses and write access must be schedule such that one transaction is initiated on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on the previous state of the sram. if both ports were deselected, the read port will take priority. if a read was initiated on the previous cycle, the write port will assume priority (since read operations can not be initiated on consecutive cycles). if a write was initiated on the previous cycle, the read port will assume priority (since write operations can not be initiated on consecutive cycles). therefore, asserting both port selects ac- tive from a deselected state will result in alternating read/write operations being initiated, with the first access be- ing a read. depth expansion the cy7c1305v25 has a port select input for each port. this allows for easy depth expansion. both port selects are sam- pled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. dese- lecting a port will not affect the other port. all pending transac- tions (read and write) will be completed prior to the device being deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedance matching with a tolerance of 10% is between 175 ohms and 350 ohms, with v ddq =1.5v. the output impedance is adjusted every 1024 cy- cles to adjust for drifts in supply voltage and temperature.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 8 of 28 application example note: 2. the above concept applies similarly to the CY7C1307V25. d q add. k/k c/c cntr. add. k/k c/c cntr. 18 72 sram #1 sram #4 v t = v ddq /2 72 18 clk/clk (output) q din add. cntr. clk/clk (input) 18 18 2 2 r=50 ? v t = v ddq /2 r=50 ? dq memory controller 18 18 cy7c1305v25 in an application
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 9 of 28 truth table [3,4,5,6,7,8,9] operation k rps wps dq dq dq dq write cycle: load address, input write data on 2 consecutive k and k rising edges. l-h h [8] l [9] d(a+00)at k(t+1) | d(a+01) at k (t+1) | d(a+10) at k(t+2) | d(a+11) at k (t+2) | read cycle: load address, read data on 2 consecutive c and c rising edges. l-h l [9] xq(a+00) at c(t+1) | q(a+01) at c (t+1) | q(a+10) at c(t+2) | q(a+11) at c (t+2) | nop: no operation l-h h h high-z high-z high-z) high-z standby: clock stopped stopped x x previous state previous state previous state previous state notes: 3. x=don?t care, h=logic high, l=logic low | represents rising edge. 4. device will power-up deselected and the outputs in a three-state condition. 5. a represents address location latched by the devices when transaction was initiated. a+00, a+01, a+10 and a+11 represents the addresses sequence in the burst. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. if this signal was low to initiate the previous cycle, this signal becomes a don?t care for this operation.fm 9. this signal was high on previous k clock rise. initiating consecutive read or write operations on consecutive k clock rises i s not permitted. the device will ignore the second read request.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 10 of 28 write cycle descriptions (cy7c1305v25) [10] bws 0 bws 1 kk comments l l l-h - during the data portion of a write sequence, both bytes (d [17:0] ) are written into the device. l l - l-h during the data portion of a write sequence, both bytes (d [17:0] ) are written into the device. l h l-h - during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. l h - l-h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. h l l-h - during the data portion of a write sequence, only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h l - l-h during the data portion of a write sequence, only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h h l-h - no data is written into the device during this portion of a write operation. h h - l-h no data is written into the device during this portion of a write operation. note: 10. assumes a write cycle was initiated per the write port cycle description truth table. bws 0 and bws 1 (cy7c1305v25) and bws 2 and bws 3 (CY7C1307V25) can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 11 of 28 write cycle descriptions (CY7C1307V25) [10 ] bws 0 bws 1 bws 2 bws 3 kk comments l l l l l-h - during the data portion of a write se- quence, all the four bytes (d [35:0] ) are writ- ten into the device. l l l l - l-h during the data portion of a write se- quence, all the four bytes (d [35:0] ) are writ- ten into the device. l h h h l-h - during the data portion of a write se- quence, only the lower byte (d [8:0] ) is writ- ten into the device. d [35:9] will remain un- altered. l h h h - l-h during the data portion of a write se- quence, only the lower byte (d [8:0] ) is writ- ten into the device. d [17:9] will remain un- altered. h l h h l-h - during the data portion of a write se- quence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will re- main unaltered. h l h h - l-h during the data portion of a write se- quence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will re- main unaltered. h h l h l-h - during the data portion of a write se- quence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will re- main unaltered. h h l h - l-h during the data portion of a write se- quence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will re- main unaltered. h h h l l-h during the data portion of a write se- quence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unal- tered. h h h l - l-h during the data portion of a write se- quence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unal- tered. h h h h l-h - no data is written into the device during this portion of a write operation. h h h h - l-h no data is written into the device during this portion of a write operation.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 12 of 28 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ?65c to +150c ambient temperature with power applied ............................................ ?55c to +125c supply voltage on v dd relative to gnd ........?0.5v to +3.6v dc voltage applied to outputs in high z state [11] ................................ ?0.5v to v ddq + 0.5v dc input voltage [11] ............................. ?0.5v to v ddq + 0.5v current into outputs (low) .........................................20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current .................................................... >200 ma hh operating range range ambient temperature [12] v dd v ddq com?l 0c to +70c 2.5 100 mv 1.4v to 1.9v electrical characteristics over the operating range [1,13] parameter description test conditions min. max. unit v dd power supply voltage 2.4 2.6 v v ddq i/o supply voltage 1.4 1.9 v v oh output high voltage i oh = -2.0 ma, nominal impedance v ddq /2+0.3 v ddq v v ol output low voltage i ol = 2.0 ma, nominal impedance v ss v ddq /2?0.3 v v ih input high voltage v ref +0.1 v ddq +0.3 v v il input low voltage [11] ?0.3 v ref ?0.1 v i x input load current gnd < v i < v ddq -5 5 ma i oz output leakage current gnd < v i < v ddq, output disabled -5 5 ma v ref input reference voltage typical value = 0.75v 0.68 0.95 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 5.0 ns cycle, 200 mhz 500 ma 6.0 ns cycle, 167mhz 450 ma 7.5 ns cycle, 133 mhz 350 ma 10 ns cycle, 100 mhz 230 ma i sb1 automatic power-down current max. v dd , both ports deselected, v in ? v ih or v in < v il f = f max = 1/t cyc, inputs static 5.0 ns cycle, 200 mhz 125 ma 6.0 ns cycle, 167mhz 100 ma 7.5 ns cycle, 133 mhz 80 ma 10 ns cycle, 100 mhz 60 ma ac input requirements over the operating range parameter description test conditions min. typ. max. v ih input high (logic 1) voltage v ref + 0.2 ? ? v il input low (logic 0) voltage ? ? v ref - 0.2 notes: 11. minimum voltage equals -2.0v for pulse duration less than 20 ns. 12. t a is the case temperature. 13. all voltages referenced to ground.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 13 of 28 switching characteristics over the operating range [1,14,15,16] cypress parameter consortium parameter -200 -167 -133 -100 description min. max. min. max. min. max. min. max. unit t power [17] v cc (typical) to the first access read or write 10 10 10 10 us cycle time t cyc t khkh k clock and c clock cycle time 5.0 6.0 7.5 10.0 ns t kh t khkl input clock (k/k and c/c ) high 2.0 2.4 3.2 3.5 ns t kl t klkh input clock (k/k and c/c ) low 2.0 2.4 3.2 3.5 ns t khk h t khk h k/k clock rise to k /k clock rise and c/c to c/c rise (rising edge to rising edge) 2.4 2.6 2.7 3.3 3.4 4.1 4.4 5.4 ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.5 0.0 2.0 0.0 2.5 0.0 3.0 ns set-up times t sa t sa address set-up to clock (k and k ) rise 0.6 0.7 0.8 1.0 ns t sc t sc control set-up to clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.6 0.7 0.8 1.0 ns t sd t sd d [17:0] set-up to clock (k and k ) rise 0.6 0.7 0.8 1.0 ns hold times t ha t ha address hold after clock (k and k ) rise 0.6 0.7 0.8 1.0 ns t hc t hc control signals hold after clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.6 0.7 0.8 1.0 ns t hd t hd d [17:0] hold after clock (k and k ) rise 0.6 0.7 0.8 1.0 ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid [15] 2.3 2.5 3.0 3.0 ns t doh t chqx data output hold after output c/c clock rise (active to active) 0.8 1.2 1.2 1.2 ns t chz t chz clock (c and c ) rise to high-z (active to high-z) [15, 16] 2.3 2.5 3.0 3.0 ns t clz t clz clock (c and c ) rise to low-z [15, 16] 0.8 1.2 1.2 1.2 ns notes: 14. unless otherwise noted, test conditions assume signal transition time of 2v/ns, timing reference levels of 0.75v,vref = 0.75 v, rq = 250 ohms, v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 15. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 100 mv from steady-st ate voltage. 16. at any given voltage and temperature t chz is less than t clz and, t chz less than t co . 17. this part has a voltage regulator that steps down the voltage internally; t power is the time power needs to be supplied above v dd minimum initially before a read or write operation can be initiated.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 14 of 28 capacitance [18] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 2.5v. v ddq = 1.5v 3 pf c clk clock input capacitance 3 pf c o output capacitance 3 pf note: 18. tested initially and after any design or process change that may affect these parameters. 1.25v 0.25v r=50 ? 5pf including jig and scope all input pulses 1304v25-2 1304v25- 3 device r l =50 ? z 0 =50 ? v ref =0.75v v ddq /2 [14] 0.75v under te st v ddq /2 device under te s t output v ddq /2 v ref v ref output zq zq (a) rq= 250 ? (b) rq= 250 ?
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 15 of 28 switching waveforms note: 19. device originally deselected. k = don?t care = undefined read/deselect sequence k a (x:0) data out rps a q(a) q(a+1) q(a+2) q(a+3) b t kh t kl t cyc t sa t ha t sc t chz t kh t kl t khk h t doh t khk h c c t co t co t khch t doh t clz q(b) q(b+1) q(b+2) q(b+3) t hc t doh deselect [19]
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 16 of 28 notes: 20. c and c reference to data outputs and do not affect writes. 21. activity on the bws x low = valid, byte writes allowed, see byte write table for details. switching waveforms k = don?t care = undefined write/deselect sequence k a data in wps a d(a) d(a+1) d(a+2) d(a+3) b t kh t kl t cyc t sa t h t sc d(b) d(b+1) t hd t sd bws x t sc t hc t kl d(b+2) d(b+3) t hc t ha [20,21]
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 17 of 28 notes: 22. read port previously deselected. 23. bws [1:0] both assumed active. switching waveforms k wps = don?t care = undefined read/write/deselect sequence k a q [x:0] rps d [x:0] d c b q(a) q(a+1) d(b) d(b+1) d(d) d(d+1) d(b+2) d(b+3) q(a+2) q(a+3) q(c) q(g+1) c c a q(c+1) q(c+2) q(c+3) d(d+2) d(d+3) [22,23]
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 18 of 28 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (vdd) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 19 of 28 is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample / preload is a 1149.1 mandatory instruction. when the sample / preload instructions are loaded into the instruction register and the tap controller is in the cap- ture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample / preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system output pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the "extest output bus tristate", is latched into the preload register during the "update-dr" state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the "shift-dr" state. during "update-dr", the value loaded into that shift-register cell will latch into the preload register. when the extest instruction is entered, this bit will directly control the output q-bus pins. note that this bit is pre-set low to enable the output when the device is powered-up, and also when the tap controller is in the "test-logic-reset" state. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 20 of 28 tap controller state diagram [24] note: 24. the 0/1 next to each state represents the value at tms at the rising edge of tck. test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 21 of 28 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [13, 25, 26] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a 2.1 v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage ?0.3 0.7 v i x input and output load current gnd v i v ddq ? 5 5 a notes: 25. overshoot: v ih (ac)< v dd +0.5v for t< t tcyc /2. undershoot v il (ac)< 0.5v for t< t tcyc /2. power-up: v ih <2.6v and v dd <2.4v and v ddq <1.4v for t<200 ms. 26. these characteristic pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 22 of 28 tap ac switching characteristics over the operating range [27,28] parameter description min. max. unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 27. parameters t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 28. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 23 of 28 tap timing and test conditions [28] (a) tdo c l =20 pf z 0 =50 ? gnd 1.25v test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov 50 ? 2.5v 0v all input pulses 1.25v
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 24 of 28 identification register definitions instruction field value description cy7c1305v25 CY7C1307V25 revision number (31:29) 000 000 version number. cypress device id (28:12) 01011010011010101 01011010011100101 defines the type of sram. cypress jedec id (11:1) 00000110100 allows unique identification of sram vendor. id register presence (0) 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and plac- es the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the bound- ary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. boundary scan order bit # bump id 0 6r 1 6p 2 6n 3 7p 4 7n 5 7r 6 8r 7 8p 8 9r 9 11p boundary scan order bit # bump id
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 25 of 28 10 10p 11 10n 12 9p 13 10m 14 11n 15 9m 16 9n 17 11l 18 11m 19 9l 20 10l 21 11k 22 10k 23 9j 24 9k 25 10j 26 11j 27 11h 28 10g 29 9g 30 11f 31 11g 32 9f 33 10f 34 11e 35 10e 36 10d 37 9e 38 10c 39 11d 40 9c 41 9d 42 11b 43 11c 44 9b 45 10b boundary scan order bit # bump id 46 11a 47 internally pre-set low 48 9a 49 8b 50 7c 51 6c 52 8a 53 7a 54 7b 55 6b 56 6a 57 5b 58 5a 59 4a 60 5c 61 4b 62 3a 63 internally pre-set low 64 1a 65 2b 66 3b 67 1c 68 1b 69 3d 70 3c 71 1d 72 2c 73 3e 74 2d 75 2e 76 1e 77 2f 78 3f 79 1g 80 1f 81 3g boundary scan order bit # bump id
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 26 of 28 82 2g 83 1j 84 2j 85 3k 86 3j 87 2k 88 1k 89 2l 90 3l 91 1m 92 1l 93 3n 94 3m 95 1n boundary scan order bit # bump id 96 2m 97 3p 98 2n 99 2p 100 1p 101 3r 102 4r 103 4p 104 5p 105 5n 106 5r boundary scan order bit # bump id ordering information speed (mhz) ordering code package name package type operating range 200 cy7c1305v25-200bzc bb165d 13 x 15 mm fbga commercial CY7C1307V25-200bzc 167 cy7c1305v25-167bzc bb165d 13 x 15 mm fbga CY7C1307V25-167bzc 133 cy7c1305v25-133bzc bb165d 13 x 15 mm fbga CY7C1307V25-133bzc 100 cy7c1305v25-1300bzc bb165d 13 x 15 mm fbga CY7C1307V25-100bzc
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 27 of 28 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. 165-ball fbga (13 x 15 x 1.4 mm) bb165d 51-85180 **
cy7c1305v2 5 cy7c1307v2 5 preliminary document #: 38-05099 rev. *a page 28 of 28 document title: cy7c1305v25 / CY7C1307V25 18mb burst of 4 pipelined sram with qdr architecture document number: 38-05099 rev. ecn no. issue date orig. of change description of change ** 107654 07/10/01 skx new data sheet *a 122949 03/14/03 rcs 1. changed status to preliminary from advanced information (all pages) 2. added ex-test feature to jtag. this implementation is backwards com- patible with the previous non-ex-test feature set. (page 19 and 24) 3. changed boundary scan order to 106 cells from 69 (page 24, 25 and 26) 4. changed cells 47 and 63 to an internal cells that are pre-set to low in the boundary scan order. note that these pins are 100% compatible with the previous scan order because they had previosly been connected to v ss . (page 25) 5. specified minimum and maximum input voltages for ac conditions. (page 12) 6. changed packaged height to 1.4 mm from 1.2 mm. (page 27) 7. changed ball diameter to 0.5 mm from 0.45 mm. (page 27) 8. added t power specification and note 17. these devices require 10 us of of v dd above v dd minimum (2.4v) before operating. (page 13)

▲Up To Search▲

Price & Availability of CY7C1307V25

	To Download CY7C1307V25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .